1. Field of the Invention
The present invention relates to a semiconductor memory device, and a method of reading data from the semiconductor memory device.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a cell array structure of a conventional ROM. The conventional ROM has a capacity of 1 M (1024×1024). The conventional ROM of FIG. 1 includes a bit cell array unit 110, a reference cell array unit 120 and a bit cell replica array unit 130, and is disclosed in U.S. Pat. No. 6,404,666.
In FIG. 1, the bit cells M0 to M15 (represented by transistors) of bit cell array unit 110 store bit cell information, i.e., store either logic low data “0” or logic high data “1” depending on whether the bit cells are coupled to virtual ground lines (lines for VGND0, VGND1, VGND2, . . . ). In other words, the drains of the transistors in bit cell array unit 110 are coupled to bit lines (lines for signals DBIT0, DBIT1, . . . ), and the sources thereof are either coupled to the virtual ground lines (see M13, M15, etc.) or open (see M1, M2, etc.). If the sources of the transistors are coupled to the virtual ground lines, logic low data (a “0”) is stored in the cells. Alternatively, if the sources are open, logic high data (a “1”) is stored in the cells. For example, bit cells M12, M13, M14, and M15 store “1”, “0”, “1”, and “0”, respectively.
Upon reading of data from bit cells, one of the virtual ground lines (lines for VGND0, VGND1, VGND2, etc.) and one of the bit lines DBIT0, DBIT1, etc. are selected in response to a ROM Y-address signal. The selected virtual ground line is provided with a ground voltage. Hence, if the sources of the transistors of the bit cell array unit 110 are coupled to the virtual ground lines, the bit lines in a pre-charged state are also discharged to a ground state and output data “0”. Additionally, one of a plurality of word lines (lines for signals VWL0, VWL1, . . . , VWL1022, and VWL 1023) is selected according to an ROM X-address signal, and the selected word line is provided with a “1”.
As one of transistors M28 through M31 is turned on by a word line turning to “1” in response to a predetermined data read clock, the bit cell replica array unit 130 receives a signal DUMVGND, which is supplied as a virtual ground voltage, and outputs a signal VDUMBIT as an enable signal of a sense amplifier (not shown).
The reference cell array unit 120 generates a reference signal which is compared with data “0” or “1” stored in the bit cells of the sense amplifier. The transistors constituting the reference cell array unit 120 have sources respectively coupled to reference signal lines REFVGND0, REFVGND1, . . . If reference signal lines are separated at an interval of 128 bit lines, the sources of the transistors of the reference cell array unit 120 are respectively coupled to reference signal lines REFVGND0 through REFVGND7. In this case, a selected reference signal, that is, one of reference signals REFBIT0 through REFBIT7, is set to have an intermediate level ranging in between “0” and “1” by a predetermined source controlled logic, and the selected reference signal with the intermediate level is output.
However, for the ROM structure of FIG. 1, since the transistors of the bit cell array unit 110 have process variations, the transistors of the reference cell array unit 120 for discharging the reference signal lines REFVGND0 through REFVGND7 have even greater process variations than those of bit cell array unit 110. These process variations in the transistors of the reference cell array unit 120 has an adverse effect on errors generated during or upon a data reading operation. In other words, if the transistors of the reference cell array unit 120 provide poor uniformity, the reference signals become unstable, and accordingly, the sense amplifier cannot perform a proper comparison with respect to the data stored in the bit cells. Therefore, the error rate of read-out data increases. Further, process variations in the transistors of the bit cell replica array unit 130 destabilize the generation of the enable signal for the sense amplifier, thus greatly affecting the error rate of read-out data.